1. Field of the Invention
The present invention relates to integrated circuit devices, and more particularly, to an integrated circuit device propagating data on a shift path previously prepared internally, such as scan designed integrated circuit devices.
2. Description of the Background Art
It is extremely difficult to observe the internal state of an integrated circuit device, particularly one having internal complex functional logics, by performing tests using only primary input/output terminals. Such difficulties are expressed by terms of "observability" and "controllability".
Controllability indicates the difficulty in controlling the internal signals of a circuit. Observability indicates the difficulty in observing the internal state of a circuit.
In order to examine whether there is a defect or not in a certain position inside the circuit, it is necessary to control the input signals applied thereto. It is also necessary to observe precisely the output obtained by the result of a predetermined input. It will be impossible to determine whether there is a fault or not in the circuit if either observability or controllability is lacking.
In an integrated circuit device having complex functional logics, there are many gates between the testing position and the primary I/O terminals. It is therefore extremely difficult to obtain satisfactory observability and controllability. Furthermore, large-scale integrated circuit devices are becoming increasingly complex according to the advance in semiconductor techniques. Meanwhile, the necessity of designing/developing various integrated circuit devices in small quantity and in a short time period is growing. In order to meet these requirements, design methods are introduced such as chip hierarchical design and cell-based method.
Regarding hierarchical design, the elements having a simple structure (for example, a logical gate) is the bottom level design unit. A plurality of design units are assembled to form one functional unit of the upper hierarchy. The functional unit of a further upper level is formed by assembling these plurality of functional units. The functional units of the lower level are taken in the abstract in the upper level, and their detail structure are not visible. By building up a more complex upper level in this manner, the design of an integrated circuit device as a final object is completed.
The cell-based method employs the concept of reusage of prior design features in addition to the hierarchical design. For example, data or the like of chips and circuit blocks having actual satisfactory operational results are stored in a library. A library is a collection of data where designs of integrated circuit devices and relating information are stored and monitored. In designing a new chip, the design data of chips with satisfactory operational results stored in the library are directly reused as one functional unit. This will simplify the design of a more large-scale integrated circuit.
It has become possible to implement individual functional units on one chip, which were formerly separated on a plurality of chips or boards, owing to the advance of semiconductor techniques in the miniaturization of circuits. This allows designing by the aforementioned cell-based method. The design time period is greatly shortened and the quality of the design has improved.
The movement to large-scale integrated circuit devices has increased the difficulty of testing the circuits as mentioned above. Therefore, the so-called testability design has become an important factor. Test execution comprises a plurality of steps such as creation of test data, carrying out the operation of the block under test by test data, output of the test results, and confirmation thereof. In accordance with the increase in scale of the circuit, the time period required for testing has increased, whereby reduction in testing time becomes an important element.
The so-called scan design method is employed to simplify the testing, which will be explained hereinafter. In scan design, shift register latches (referred to as SRL hereinafter) are provided at internal observation points (the location where the output is to be observed) and control points (the location where the input is set) in the integrated circuit. By connecting a plurality of SRLs in series, a shift path (referred to as "scan path" hereinafter) is formed where data can be propagated therethrough.
The desired data is set at the SRL of the control point by externally applying data to the scan path to be propagated serially within the scan path. The stored data in each SRL is applied to the circuit under test. The output is provided to the SRL of each observation point and stored therein. The stored data of the SRL is transmitted again on the scan path serially to be provided externally as a serial signal from the output terminal. Observability and controllability in the profound locations of the integrated circuit device can be obtained by providing such a scan path.
This scan design method handles data in time series. The scan length increases due to the large-scalarization of the integrated circuit device. Accordingly, the testing time will also increase.
FIG. 25 is a graph showing the estimation of the testing time when the scan path length increases. (Takeshi Hashizume et al. "Cell-Based Test Design Method" 1989 International Test Conference Proceedings pp. 909-916). Referring to FIGS. 26 and 27, the chip model 105 of this estimation comprises n model units (MU1) 104 and one model processor (MC1) 106.
One model unit 104 comprises 3 logic blocks (MB1) 101, one 512w (word).times.16b (bit) ROM block (MB2) 102, and one 250w.times.8b RAM block (MB3) 103.
The major features of MB1, MB2, MB3 and MC1 are as shown in FIG. 27. In this test, SRLs are provided only at the input terminal of each circuit block for reducing the overhead (area and propagation delay) of the testing circuit. Accordingly, the scan path length of each block is equal to the number of input terminals of each block (the number of SRLs connected in series).
The number of input terminals of one model unit 104 is 149 (40.times.3+10+19). The number of inputs of MC1 is 40. One model chip comprises n model units 104 and one model processor 106, as stated before. The scan path of each model unit and model processor within model chip 105 are all connected in series. In other words, there is only one scan path formed in model chip 105. Therefore, the scan path length of this model chip is 149.times.n+40.
The testing time shown in FIG. 25 is represented in the graph in comparison with the circuit complexity (the number of transistors). The circuit complexity of the chip is {(8k+8K+16K).times.n+50K}. Both the circuit complexity of the chip and the scan path length are proportional to n. It is considered that the relationship between the scan path length and the testing time is similar to that of the graph in FIG. 25.
It is appreciated from FIG. 25 that the testing time is proportional to the scan path length. In the testing of integrated circuits, it is required that the time for testing and the number of test pins are reduced to shorten the development time period and the inspection time at shipment. To meet these requirements, the method of dividing the scan path and carrying out the input/output of data using a multiplexer (MUX) by single input and output pins has been employed.
Referring to FIG. 28, integrated circuit 1 comprises functional modules 3a, 3b, 3c and a multiplexer 5. The functional module comprises the aforementioned ROM, RAM or processor.
SRLs 4a-4f are connected to the input and output terminals of functional module 3a. Functional module 3a and SRLs 4a-4f form module 2a.
SRLs 4g-4k are connected to the input and output terminals of functional module 3b. Functional module 3b and SRLs 4g-4k form module 2b.
SRLs 4l-4r are connected to the input and output terminals of functional module 3c. Functional module 3c and SRLS 4l-4r form module 2c.
SRLs 4a-4f are connected in series to form one scan path. The input of SRL 4a is connected to scan-in (SI) terminal 6. The output of SRL 4f is connected to MUX 5. In a similar manner, SRLs 4g-4k form one scan path with the input thereof connected to SI terminal 6 and the output thereof connected to MUX 5. SRLs 4l-4r are also connected in series to form one scan path, with the input thereof connected to SI terminal 6 and the output thereof connected to MUX 5.
MUX 5 is provided with selecting signal input terminals 8a and 8b, where the output thereof is provided from scan-out (SO) terminal 7. Selecting signal input terminals 8a and 8b are input terminals applied with selecting signals for selecting one of functional modules 3a, 3b, 3c as the block to be tested. The selecting signal comprises 2 bits since there are 3 selection objects.
Referring to FIG. 28, the operation of integrated circuit 1 at the time of functional testing is described hereinafter. The functional testing of integrated circuit 1 is accomplished by carrying out the functional testing of functional modules 3a-3c individually. Sufficient test pattern data for testing the functions are prepared in advance regarding functional modules 3a-3c.
The functional testing of functional module 3a will be taken as an example. A 2-bit value is set at selecting signal input terminals 8a and 8b for indicating to MUX 5 that the output of SRL 4f is to be provided from SO terminal 7.
Input data for functional testing of functional module 3a is applied in series from SI terminal 6. The input data is propagated on the scan path of SRLs 4a-4f in sequence to be set in the SRL connected to the input terminal of the functional module 3a. This allows the external desired data to be applied to the input terminal of the internal functional module 3a of the integrated circuit.
Functional module 3a is responsive to the input value to provide the result at the output terminal. The output result is stored in the SRL connected to the output terminal of functional module 3a. The data held in SRL is propagated in sequence to the scan path and MUX 5 to be serially provided from SO terminal 7.
The aforementioned operation is carried out for all test patterns of functional module 3a to complete the functional testing of functional module 3a. Similar functional testings are carried out for functional modules 3b and 3c.
Considering the creation of a library, functional module 3a and SRLs 4a-4f for testing functional module 3a are often bundled together to be effectively designed as a new module 2a. The other functional modules 3b and 3c are also often designed as modules 2b and 2c incorporating the scan path for testing.
With reference to FIG. 29, an example applying the conventional scan design of FIG. 28 to the hierarchical design will be explained. An integrated circuit device having such hierarchical testing circuits is disclosed in Japanese Laying-Open No. 62-93672, for example. Referring to FIG. 29, the hierarchical integrated circuit 1b comprises modules 1a, 2d, and 2e, and MUX 5b.
Module 1a is identical to the integrated circuit 1 of FIG. 28. Integrated circuit 1b comprises the integrated circuit 1 of FIG. 28 as one module 1a. A new function of integrated circuit 1b is implemented by arranging module la with the other individual modules 2d and 2e on integrated circuit 1b. In FIG. 29, only the scan path and the block under test associated with MUX 5b are shown for convenience of description.
Module 1a further comprises lower level modules 2a, 2b and 2c, and MUX 5a for selecting one of the three modules for testing. Module 2a comprises a functional module not shown, and SRLs 4a-4f connected serially. Each of SRLs 4a-4f is connected to the input/output terminals of the functional module not shown. The input of SRL 4a is connected to SI terminal 6a of module 1a, and the output of SRL 4f is connected to MUX 5a.
In a similar manner, module 2b comprises a functional module not shown and SRLs 4g-4k. Module 2c comprises a functional module not shown and SRLs 4l-4r. SRLs 4g-4k and SRLs 4l-4r are respectively connected in series to form a scan path, with the inputs thereof both connected to SI terminal 6a and the outputs thereof both connected to MUX 5a.
MUX 5a is provided with selecting signal input terminals 8a and 8b, with the output thereof connected to SO terminal 7a. Selecting signal input terminals 8a and 8b are also connected to selecting signal input terminals 8a' and 8b' of integrated circuit 1b. SO terminal 7a of module 1a is connected to MUX 5b of integrated circuit 1b.
Similarly to modules 2a, 2b and 2c, module 2d comprises a functional module not shown, and SRLs 4s-4u connected serially. SRLs 4s-4u form a scan path with the input thereof connected to SI terminal 6b and the output thereof connected to MUX 5b. SRLs 4s-4u are connected to the I/O terminals of the functional module not shown of module 2d.
In a similar manner, module 2e comprises a functional module not shown, and SRLs 4v-4x connected serially. SRLs 4v-4x form a scan path with the input thereof connected to SI terminal 6b and the output thereof connected to MUX 5b.
MUX 5b is provided with selecting signal input terminals 8c and 8d for selecting one of modules 1a, 2d and 2e. The data selected by MUX 5b is provided to SO terminal 7b.
Referring to FIG. 29, the operation in functional testing of each functional module of the hierarchical integrated circuit 1b will be explained. Via selecting signal input terminals 8c and 8d, MUX 5b is externally applied with a selecting signal for selecting one of modules 1a, 2d and 2e.
For example, it is assumed that module la is selected by the selecting signal. The output of SO terminal 7a is provided to SO terminal 7b via MUX 5b. Module 1a comprises three lower level modules 2a, 2b, and 2c. One of the three modules must be selected at the time of testing. A selecting signal for specifying this selection of the module is applied to MUX 5a via selecting signal input terminals 8a and 8b.
It is assumed that module 2a is selected, for example. A scan path from SI terminal 6b to SO terminal 7b through module 2a, MUX 5a, and MUX 5b is formed.
With module 2a selected, the test pattern data from SI terminal 6b is set in SRLs 4a-4f. The functional module of module 2a is operated by the test data. The result of the testing is stored in the SRL of 4a-4f connected to the output of the functional module not shown. The output result is again transmitted on the scan path to be provided from SO terminal 7b in series. The testing of module 2a is completed by carrying out functional testing regarding all the test patterns of the functional module of module 2a.
In a similar manner, modules 2b and 2c are each selected by changing the signal applied to selecting signal input terminals 8a' and 8b'. The testing of module 1a is completed by carrying out the testing regarding each module.
After the testing of module 1a is completed, the signal applied to selecting signal input terminals 8c and 8d are changed, whereby either module 2d or 2e is selected as the block to be tested. Similarly to module la, testing of either of module 2d or 2e is carried out. In this case, it is not necessary to select the scan path in module 2d, for example, because modules 2d and 2e only have a single scan path.
As said in the foregoing, functional testing of integrated circuit 1b is completed by carrying out testing regarding all modules, including the lower level modules in a module.
In the case where integrated circuit 1b is developed incorporating integrated circuit 1 of FIG. 28 directly as module 1a, the following problems occur.
Hierarchical module 1a has its physical layout determined under a state where signal wiring is allocated for functional testing of each module 2a, 2b and 2c. This design data is stored in a library where the contents can not be modified. The modification of design pattern of module 1a from integrated circuit 1 in incorporating module 1a to integrated circuit 1b is difficult and does not agree with the concept of hierarchical design. It is not basically allowed because the operational characteristics and the like can not be guaranteed after the modification of the pattern.
For example, the design of MUX 5a or selecting signal input terminals 8a and 8b can not be modified in module 1a. This means that the allocation of the module is limited. It is necessary to provide many selecting signal input terminals such as 8a' and 8b' for specifying the selection in the MUX circuit every time an upper level integrated circuit is hierarchically designed. The addition of such terminals will not only complicate the structure of the upper level functional modules, but also decrease the effectiveness of test execution. The number of pins of the chip is also limited, so many pins can not be provided for the purpose of testing.
It is necessary to provide testing circuits considering the hierarchical design in each functional module. FIG. 30 shows such a circuit. The circuit diagram of FIG. 30 is produced by the inventor of the present invention according to the invention disclosed in Japanese Patent Laying-Open No. 61-99875, for example.
Referring to FIG. 30, integrated circuit 1 includes three modules 21, 2b and 2c.
Module 2a includes functional module 3a, SRLs 4a-4f connected to the I/O terminals of functional module 3a in series to form one scan path, and MUX 5a having one input connected to the input terminal of SRL 4a and the other input connected to the output terminal of SRL 4f, for selectively providing the input from SI terminal 6 and the signal via SRLs 4a-4f, in response to the selecting signal applied from selecting signal input terminal 201.
In a similar manner, module 2b includes functional module 3b, SRLs 4g-4k each connected to the I/O terminals of functional module 3b and connected in series to form one scan path, and MUX 5b having one input connected to the output of MUX 5a and the other input connected to the output of SRL 4k, for selectively providing the signal applied from MUX 5a and the signal applied via SRLs 4g-4k in response to the selecting signal applied from selecting signal input terminal 202.
Module 2c includes functional module 3c, SRLs 4l-4r each connected to the I/O terminals of functional module 3c and connected in series to form one scan path, and MUX 5c having one input connected to the output of MUX 5b and the other input connected to the output of SRL 4r, for selectively providing the signal applied from MUX 5b and the output of SRL 4r to SO terminal 7 in response to the selecting signal applied from selecting signal input terminal 203.
In integrated circuit 1 of FIG. 30, the scan path of each modules 2a-2c and the bypass path bypassing each scan path can be selected by MUXs 5a-5c in response to the selecting signal applied from selecting signal input terminals 201-203. It is possible to determine whether to test or not each module by the signal applied to selecting signal input terminals 201-203. Thus, the testing time can be reduced because the scan path length is shortened.
The integrated circuit with such configuration has the following problems. The selection of each scan path is carried out by the signal applied to selecting signal input terminals 201-203. The number of necessary selecting signal input terminals is equal to the number of scan paths in the chip. The number of pins for applying the selecting signal increases linearly according to the number of functional modules within the chip. It has become actually impossible to create such an integrated circuit regarding large-scale integrated circuits.
As shown in FIG. 31, the approach of providing a decoder 91 to determine as the block under test which of the functional modules of the integrated circuit is to be selected can be taken, for avoiding the aforementioned problem. The testing circuit employing a decoder is disclosed in the aforementioned Japanese Patent Laying-Open No. 62-93672, U.S. Pat. No. 4,701,921, or the like. By providing decoder 91, there is an advantage that the number of pins for selecting the module under test does not have to be significantly increased.
However, such a method requires the provision of test circuit blocks including decoder 91. This imposes a new load of considering the design, allocation, wiring, and the like of the test circuit block for designers in designing the chip. It is also necessary to gather the selecting signal lines in the decoder of the test circuit block. This will reduce layout efficiency due to increase of wiring region and the like.
FIG. 32 shows a schematic diagram of an integrated circuit in hierarchical design, using the integrated circuit provided with a decoder as a functional module. Referring to FIG. 32, integrated circuit 1b includes modules la, and 2a-2d. Module 1a further includes lower level modules 2e-2j. Each of modules 2a-2j has a scan path of a structure identical to that of modules 2a-2c of FIG. 31.
Module 1a further includes a decoder 91a for specifying whether or not to select each of modules 2a-2j as the block under test. Each of modules 2e-2j is connected to decoder 91a.
Integrated circuit 1b further includes a decoder 91b for deciding to select or not modules 1a, and 2a-2d as the block under test. Decoder 91a of module 1a, and modules 2a-2d are connected to decoder 91b. Accordingly, wiring for applying selecting signals are gathered in the periphery of decoder 91b. This will lead to a problem that the efficiency of the layout will be lowered according to the increase in scale of the circuit and hence in the wiring region.
Testing circuit techniques that can solve the above mentioned problem is described in U.S. Pat. No. 4,872,169, and in "DESIGNING AND IMPLEMENTING AN ARCHITECTURE WITH BOUNDARY SCAN", IEEE Design & Test of computers, February 1990 pp. 9-19. With the testing circuit techniques described in these articles, the selecting data is propagated by each scan path. Each scan path is provided with registers serially, where the selecting data is held. The selecting data held in each register is provided to each MUX directly or via a latch to control the switching of each MUX. Each MUX is responsive to the applied selecting data to select the output data of the corresponding scan path, or the input data of the corresponding scan path for providing the selected data to the next testing circuit.
In accordance with the above mentioned testing circuit techniques, the number of signal lines and the signal input/output pins can be reduced because the selecting data is propagated through one data propagation path. Furthermore, the cluster of signal wires, as shown in FIG. 32, is prevented. However, the provision of registers for holding selecting data in each scan path on the data propagation path implemented with each scan path will cause wasteful bits at the time of test data propagation to increase the bit length of the test data propagation path. This will lengthen the propagation time of the test data to increase the testing time. Because each of the above mentioned registers is not bypassed by a MUX, each register will function as a wasteful bit even in modules which are not selected as the object of testing. The increase in testing time is not so serious in the case the number of functional modules to be tested is small. However, in the present situation where large scale integrated circuit devices are obtained and many functional modules are mounted on one chip, the increase in testing time of each register is accumulated to become a critical problem.
The design method of hierarchical design or cellbased method becomes a necessity in designing large-scale integrated circuit devices, as mentioned above. It is therefore necessary to allow the design data of functional modules to be used in the design of new integrated circuits without modification, and reducing the load at the time of design for testing or reducing the time for testing. It is also necessary to reduce the required chip area for testing.